Hi! I have a problem, but I'm not that good in computer architecture (and organisation).
If we look parallel environment - shared memory model, bus based (so every processor has it's on cache, but main memory is shared). For cache coherency we need some mechanism, a protocol. There are numerous protocols, but I am interested in Write-Broadcast (Write-Update) Protocol. Today, usualy, Write-Invalidate Protocol is used, and transition diagramms for cache states can be seen on this
page (slide 14).
What would be transition diagram for the Write-Broadcast Protocol (if we analyze all activities that change cache block status) based on bus requests and acitivities? What would be transition diagram for write-broadcast protocol based on processor requests and activities? Is there a need for Dirty and Clean states for memory block?
Thanks. Спасибо.
