IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS CALL for PAPERS
Special Issue on Multiple-Valued Logic and Applications Guest editors
Vincent Gaudet, University of Waterloo,
vcgaudet@uwaterloo.ca Jon T. Butler, Naval Postgraduate School,
jbutler@nps.edu Robert Wille, University of Bremen,
rwille@informatik.uni-bremen.de Naofumi Homma, Tohoku University,
homma@aoki.ecei.tohoku.ac.jp Scope, purpose and submission procedure Multiple‐valued logic (MVL) is the broad field of study of circuits and systems in which information is carried by
more than two values, or where information is represented in unconventional, i.e., non‐binary‐weighted ways.
There have been many recent MVL innovations that are relevant to circuit and system design, including:
memory cells that store multiple bits per cell, MVL approaches to the design and modeling of
nanotechnologies, and multiple-valued decision diagrams. For this Special Issue on MVL and Applications, you
are invited to submit an article on an emerging subject in the area of MVL, as detailed below. Articles should
be addressed primarily to the diverse readership of JETCAS.
Prospective authors should submit PDF versions of their papers following the instructions provided on the
JETCAS web-site:
http://jetcas.polito.it/general.html. Submitted manuscripts should not have been previously
published nor should they be currently under consideration for publication elsewhere. Manuscripts will
undergo a peer review process according to the standard IEEE publication policy.
Topics of interest Circuit/Device Implementation
Multi-bit per cell logic & memory
Multiple-Valued Decision Diagrams
MVL Aspects of Nanotechnology
Quantum Computing/Reversible Computing
System-on-Chip Technology
Test and Verification
VLSI Architecture and Computing
Important dates • Manuscript submissions due February 1, 2015
• First round of reviews completed May 1, 2015
• Revised manuscripts due June 1, 2015
• Second round of reviews completed July 1, 2015
• Final manuscripts due August 1, 2015
Request for information
vcgaudet@uwaterloo.cahttp://jetcas.polito.it